1 Field of the Invention
The present invention relates generally to digital-to-analog conversion and, more particularly, to an apparatus for digital-to-analog conversion via multiple stages of delta-sigma modulation.
2. Discussion of the Related Art
Base stations for wireless telephone networks typically have a plurality of transmitters, each transmitter being able to transmit only one carrier at a time. It currently is not feasible for a transmitter to transmit multiple carriers simultaneously because digital-to-analog converters (DACs) currently utilized in the transmitters do not provide enough bandwidth with signal-to-noise ratios (SNRs) high enough to support multiple transmissions and still comply with FCC noise limitations. Thus current methods for converting an RF multi-carrier signal for transmission involve breaking up the RF signal band into smaller sub-bands. Each sub-band is converted to an analog signal using a digital-to-analog converter (DAC). The frequency value of the DAC output is adjusted using a conventional mixer with a local oscillator (LO) source. LO sources and mixers, however, can drift in frequency with changes in temperature.
There is a need for a low-cost signal modulator for processing RF multi-carrier waveforms for transmission. It would be desirable for such a modulator to operate over a wide bandwidth yet occupy little circuit “real estate”. Delta-sigma modulation techniques are known in connection with signal conversion; however, delta-sigma modulation has been impractical for commercial RF applications such as cellular networks. For example, a delta-sigma modulator with sixteen-bit input samples implemented in indium phosphide (InP) high-speed digital logic circuitry would occupy a relatively small amount of circuit “real estate”. Fabricating such circuitry would be prohibitively expensive, however, because of the high cost, and low circuit yield of indium phosphide wafer production. In contrast producing a sixteen-bit delta-sigma modulator using slower complementary metal-oxide semiconductor (CMOS) technology would cost less than indium phosphide, at a higher percent transistor yield, per wafer. Such a CMOS-based chip, however, would require operation at clock rates which are beyond state of the art for commercial CMOS technology.